SSIRST=0, RTRG=00, AUCKE=0, RIE=0, RFRST=0, TTRG=00, TIE=0, TFRST=0
FIFO Control Register
| RFRST | Receive FIFO Data Register Reset 0 (0): Clears the receive data FIFO reset. 1 (1): Initiates the receive data FIFO reset. |
| TFRST | Transmit FIFO Data Register Reset 0 (0): Clears the transmit data FIFO reset. 1 (1): Initiates the transmit data FIFO reset. |
| RIE | Receive Interrupt Enable NOTE: RXI can be cleared by clearing either the RDF flag (see the description of the RDF bit for details) or RIE bit. 0 (0): Receive data full interrupt (RXI) request is disabled 1 (1): Receive data full interrupt (RXI) request is enabled |
| TIE | Transmit Interrupt Enable NOTE: TXI can be cleared by clearing either the TDE flag (see the description of the TDE bit for details) or TIE bit. 0 (0): Transmit data empty interrupt (TXI) request is disabled 1 (1): Transmit data empty interrupt (TXI) request is enabled |
| RTRG | Receive Data Trigger Number 0 (00): 1 1 (01): 2 2 (10): 4 3 (11): 6 |
| TTRG | Transmit Data Trigger Number NOTE: The values in parenthesis are the number of empty stages in SSIFTDR at which the TDE flag is set. 0 (00): 7 (1) 1 (01): 6 (2) 2 (10): 4 (4) 3 (11): 2 (6) |
| SSIRST | SSI soft ware reset 0 (0): Clears the SSI software reset. 1 (1): initiates the SSI software reset. |
| AUCKE | Oversampling Clock Enable 0 (0): The oversampling clock is disabled. 1 (1): The oversampling clock is enabled. |